1. Field of the Invention
The present invention relates to a timesharing internal bus, particularly for a non-volatile memory, that transfers streams of data including data originating from the memory; codes related to the wiring of paths; configuration data; information of internal points; etcetera. The present invention more particularly relates to a particular architecture of the memory, which allows better management of the information streams of the memory device.
2. Discussion of the Related Art
In non-volatile memories, such as for example EPROMs, EEPROMs, and FLASH memories, an architecture is generally known which includes a memory matrix with paths directed toward the I/O pads arranged on one side of the device for data reading/writing, while the input (address) pads are placed in a different position, for example on the opposite side, in order to optimize the area of the device.
These input (address) pads stimulate various processes of the memory, whereas the I/O pads collect data in output or provide the data to be written to the memory.
Often it is necessary to transmit outside the memory device, internal situations of the memory (for example for testing or troubleshooting), related to circuit parts that are possibly even quite distant from the I/O terminals.
It is also necessary to reconfigure the read/write paths and to provide particular operating modes.
Due to the considerable distance between the parts, which are typically arranged opposite each other, every form of xe2x80x9cdedicatedxe2x80x9d transmission entails increases in space occupation and management of the memory device.
Accordingly, in order to obtain the desired signals, long connecting lines extending from one side of the memory to the other are necessary. Each connecting line, despite performing functions that are indispensable for the functionality of the circuit, still entails an expenditure of area and may create reliability problems.
Indeed, the larger the memory device, the longer said connecting lines must be, with problems of area occupation, management complexity, and possibility of malfunction.
The aim of the present invention is therefore to reduce the number of connecting lines coupled between the pads on one side and the other of the memory device, in order to reduce the area of the device.
Within the scope of this aim, an object of the present invention is to optimally utilize the internal transmission resources that intrinsically exist and are indispensable.
Another object of the present invention is to provide a data transmission system that is compact and flexible.
Another object of the present invention is to standardize the functional modes of the memory device and to increase its potential.
Another object of the present invention is to provide an architecture of the memory device that is highly reliable and relatively easy to provide at competitive costs.
This aim, these objects, and others which will become apparent hereinafter are achieved by a non-volatile memory device, characterized in that it comprises an internal bus for the transmission of data and other information of said memory to output pads; timer means; and means for enabling/disabling access to said bus; said timer means timing said internal bus to reroute information signals of the memory device that originate from local auxiliary lines onto said internal bus when said bus is in an inactive period during a normal cycle for reading data of the memory, said timer means driving said enabling/disabling means to allow/deny access to said internal bus on the part of said information signals or of the data from or to the memory.
One embodiment of the present invention is directed to a non-volatile memory device. The non-volatile memory device includes an internal bus for the transmission of data and other information of said memory device to output pads, a timer, means for enabling and for disabling access to the bus. The timer controls the internal bus to reroute information signals of the memory device that originate from local auxiliary lines onto said internal bus when said internal bus is in an inactive period during a normal cycle for reading data of the memory device. The timer controls the enabling and disabling means to allow access to the internal bus by the information signals and to deny access to the internal bus by the data in the first mode of operation, and said timer controlling the enabling and disabling means to allow access to the internal bus by the data and deny access to the internal bus by the information signals in a second mode of operation.
Another embodiment of the present invention is directed to a data transmission method for a non-volatile memory device having a timer, a time sharing internal bus, and an enabling/disabling circuit that controls the access by information signals of the device and of memory data to the internal bus. The method includes steps of detecting an address transition signal at an input to the timer, presetting, by virtue of the timer, signals for correctly reading and capturing the memory data, preventing access of the memory data to the internal bus, during the first step of a reading cycle of the memory during which the memory data is not ready for proper reading, transmitting, on the internal bus, the information signals during the first step of the reading cycle, after transmitting said information signals, during a second step of the reading cycle, preventing access of the information signals to the internal bus, and transmitting, on the internal bus, said memory data during the step of the reading cycle.
Another embodiment of the present invention is directed to a memory having a memory module that stores memory data, an input/output port that receives memory data to be written to the memory and provides memory data read from the memory, an internal bus coupled to the input/output port, at least one auxiliary input line that contains at least one information signal, and a control circuit that controls the memory to operate in one of at least a first mode of operation and a second mode of operation, such that in the first mode of operation the input bus is coupled to the auxiliary input line to receive the information signal, and in the second mode of operation, the input bus is coupled to the memory module to transmit memory data between the input bus and the memory module.
Another embodiment of the present invention is directed to a memory comprising a memory module that stores memory data, an input/output port that receives memory data to be written to the memory and provides memory data read from the memory, an internal bus coupled to the input/output port, at least one auxiliary input line that contains at least one information signal, and means for controlling the memory to operate in one of at least a first mode of operation and a second mode of operation such that in the first mode of operation an input bus is coupled to the auxiliary input line to receive the information signal, and in the second mode of operation, the input bus is coupled to the memory module to transmit memory data between the input bus and the memory module.
Another embodiment of the present invention is directed to a method of transferring data in a memory having an input bus, a storage module, and an auxiliary input line. The method includes steps of coupling the auxiliary input line to the input bus, transferring data from the auxiliary input line to the input bus, coupling the input bus to the memory module, and transferring data between the input bus and the memory module.